The present embodiments relate to electronic circuits and are more particularly directed to selectable application of an offset to a dynamically controlled voltage supply.
Electronic circuits are prevalent in numerous applications and are used in devices in personal, business, and other environments. Demands of the marketplace affect many design aspects of these circuits, including device size, complexity, efficiency, performance, and cost. These aspects are often important in various devices. By way of example, the mobile phone industry is transitioning from devices that are voice oriented to devices that are multimedia oriented, and multimedia applications typically integrate high performance processing cores. As a result, the above-mentioned aspects of size, complexity, efficiency, performance, and cost manifest themselves in various areas, including energy consumption, speed capability, and battery lifetime. These areas are also a concern in various other electronic devices, particularly where energy is a concern such as in other battery-powered applications. Thus, to maintain pace with marketplace demands and supplier goals for these devices, considerations with respect to these factors are of paramount interest.
With the developments described above, integrated circuit, or “chip”, design in the current state of the art often uses various criteria to determine a nominal level of voltage supply for the device, with a corresponding clock speed specification then determined from that nominal voltage supply. For example, some manufacturers develop a yield distribution curve, often in the shape of a Gaussian distribution (i.e., bell curve). Due to manufacturing variations, each chip in a group of chips will fall somewhere along this curve in terms of the quality of the overall silicon of the device. With this curve, for purposes of developing a speed specification for the entire group of chips, the weakest acceptable device is then tested with a power supply providing a pin-level voltage at which the device is predicted to perform over an acceptable period of time. For example, in current technology, such voltage may be on the order of 1.2 volts for a device, such as a digital signal processor, to operate reliably for a predicted period of seven years (where the use of seven years is only by way of example). This voltage, often referred to as the nominal voltage, is typically determined from various attributes of the device, such as the voltage susceptibility of the transistor gate oxides (or insulators) on the chip, as is often constrained by the gate oxide thickness. Thus, this nominal voltage becomes a constraint on the amount of voltage applied to all chips in the group.
Also in connection with determining a nominal voltage supply, the prior art recognizes that the chip's voltage supply typically is a device external from the chip, and that voltage supply has a corresponding level of tolerance. For example, a voltage supply may be said to provide 1.2 volts, with a tolerance of 10%. Thus, the actual voltage provided by the supply may be anywhere in the approximate range of 1.08 volts to 1.32 volts. Accordingly, with the above voltage application and speed specification procedure, often the chip designer is required to assume a worst case scenario in terms of potential supply voltage, meaning in the present case the minus 10% voltage tolerance and a resultant output of the voltage supply of only 1.08 volts. In another respect, the prior art approach contemplates voltage loss between the power supply and the ultimate transistors of the chip's processing core(s). For example, the voltage supply as provided external from the chip traverses conductors between the voltage supply and the chip and they impart line losses due to the various attributes of the conductor lines (e.g., trace resistance and their tolerances). As another example, there may be line losses and tolerances internal to the chip, where those losses are incurred as the voltage is routed from the chip's external pins to the transistors of the chip's processing core(s). As still another example, temperature variations may cause a resistance change and, hence, a change in the voltage that ultimately reaches the chip's processing core(s).
As a result of the preceding, in part of the prior art the designer that is to determine a clock speed specification for a chip is often required to account for the worst case scenario for all of the possible voltage losses, by testing the corresponding chip core at a supply voltage level that includes all those losses. For instance, with a nominal voltage of 1.2 volts, then with these additional considerations there could be a worst-case-scenario loss of 0.2 volts before that nominal voltage reaches the processing core(s), coupled with the example above of 10% (i.e., 0.1 volt) loss from the power supply tolerance. In this case, only 0.9 volts actually reaches the processing core(s). Thus, the designer applies this worst-case 0.9 volts directly to the chip core and evaluates the speed of operation that the core can reliably provide at that voltage. Of course, this speed will be less than that which would be achieved in an ideal (i.e., lossless) case, where 1.2 volts would be applied to the core. Thus, this resulting test-speed becomes the specification speed for the device. Hence, assuming the device is then used properly per its specification, it is thereafter implemented into a system by a vendor, installer, OEM or the like, and clocked at this worst-case speed while connected to the corresponding nominal voltage (e.g., 1.2 volts). Lastly, note that in one approach, a voltage supply with a smaller tolerance may be used so as to gain back some of the difference in test-confirmed clock speed as between the ideal case and the higher tolerance case, but of course a lower tolerance voltage supply is more costly and thereby increases the overall system cost.
As yet another consideration with respect to the preceding, note that the prior art worst-case-scenario approach is often used to define the nominal voltage and test-confirmed clock speed as specifications for all chips in a group. More particularly, once the required nominal voltage is determined, it is applied to the weakest chip in the group and the speed attainable at that voltage becomes the specification speed for that chip. However, in the prior art, often this worst-case performance is then used as a limit for all chips in the same group as the weakest chip. Thus, chips in the same group, but that are better silicon than the weakest silicon device or that incur lesser losses than that anticipated in the worst-case scenarios, are necessarily constrained to perform at the test-confirmed clock speed in response to the nominal voltage as determined based on worst case conditions including the lesser performing chip. Thus, the above-described limitations are imposed on entire groups of chips rather than just single tested chips.
In view of the above, certain patent applications describe various improvements to the prior art. For example, U.S. application Ser. No. 11/139,452, entitled “Integrated Circuit With Dynamically Controlled Voltage Supply”, was filed May 27, 2005 and is incorporated herein by this reference. With respect to U.S. patent application Ser. No. 11/139,452, it describes, among other things, an integrated circuit with a core as well as a speed capability indicator circuit that mimics a part of the core and in doing so produces an output signal that demonstrates a potential clock speed at which the core could operate at the present supply voltage. If that potential clock speed is higher than the actual core clock speed, it is recognized that in effect the voltage then being provided to the core is in excess of what they core truly requires to operate at the current actual clock speed, since the mimic circuit is able to achieve a faster speed at the same voltage. Thus, a detailed controller in the referenced application may dynamically adjust the system voltage, by lowering the system bias voltage and/or raising the system back bias voltage, thereby permitting the core to remain operating properly at its actual clock speed while using less power as provided from the adjusted system bias voltage(s). As another example, U.S. application Ser. No. 11/045,222, entitled “Adaptive Voltage Control For Performance And Energy Optimization”, was filed Jan. 28, 2005 and is also incorporated herein by this reference. With respect to U.S. patent application Ser. No. 11/045,222, it describes, among other things, an integrated circuit chip that includes a reflex module, and that module includes speed capability indicator circuits or tracking elements in the form of a NAND oscillator and a NOR oscillator. Each oscillator provides a respective oscillator frequency in response to factors influencing the entire chip (e.g., voltage, process or manufacturing factors, temperature, leakage), thereby indicating the effect of those factors on the oscillators as well as how those effects impact the remainder of the chip. If the oscillator frequencies differs from the critical path frequency, possibly with scaling that is achieved by way of multipliers, then a dynamic adjustment in system voltage may be made based on that difference and thereby providing more efficient operation. Note in this latter case that the NAND oscillator is more sensitive to the effect of the environmental factors as they influence NMOS devices on the chip, and the NOR oscillator is more sensitive to the effect of the environmental factors as they influence PMOS devices on the chip.
By way of further background, the present inventors have recognized that a portion of the core in many contemporary integrated circuits typically includes a memory, and more particularly in many instances the memory includes static random access memory (“SRAM”). As known in the memory art, SRAM is a type of memory that is faster and more reliable than the more common dynamic RAM (“DRAM”), and the data stored in SRAM does not need to be refreshed like it does in DRAM. With the recognition of SRAM in a core, the present inventors also have discovered a potential drawback in the application of the above-introduced dynamically adjustable voltage systems to SRAM. Specifically, the above-described dynamic voltage approaches are well-suited for CMOS devices. However, many SRAMs do not operate in the traditional sense of CMOS and as such there are considerations that differ with respect to dynamically altering the SRAM voltage supply. Specifically, in typical CMOS operation, either a p-channel transistor is enabled and provides a voltage in one state of operation while a complementary n-channel transistor is disabled, or an n-channel transistor is enabled and provides a voltage in another state of operation while the complementary p-channel transistor is disabled. In contrast, in an SRAM typically a larger periphery n-channel transistor is connected to each bit line and is required when writing to an SRAM cell to in effect overpower an enabled p-channel transistor in the cell so as to discharge the drain of that p-channel transistor, only after which if successfully discharged is the p-channel transistor is then disabled. Moreover, in the case of the larger n-channel transistor, the difference between the cell supply voltage and the n-channel transistor source voltage must be sufficiently large so as to leave a sufficient voltage above the lower cell supply voltage (e.g., ground) to achieve this discharge, that is, to trip the state of the cell. This difference is affected when applying one of the above-described dynamically adjustable voltages to the n-channel transistor gate and, indeed, in some cases it has been observed that a source voltage of less than ground would be theoretically required to trip the cell for certain dynamically adjustable voltages at the transistor. However, such below-zero source voltages are unacceptable given that the source voltage is in fact tied to ground; thus, a measure is defined as the minimum voltage required at the source terminal of the larger n-channel write transistor and at which the bit cell trips, and this minimum voltage is referred to herein as the device's trip voltage, or Vtrip. In current state of the art technology in the area of 100 nm CMOS devices, then the supply voltage is approximately 1.2 volts at the pins of the chip, which typically translates to a supply of approximately 1.08 volts at the SRAM cell transistors. Thus, there is only 1.08 volts across the CMOS cell transistors relative to ground, and if dynamically adjustable voltages are applied to the gate of the above-described n-channel transistor, then as observed there is the possibility for these relatively low voltage supply values that the cell will not trip state.
Given the preceding, it has been recognized in connection with the present inventions that if one of the above-introduced dynamic voltage changing approaches is implemented in connection with the cells of an SRAM, then there is the possibility that the system voltage may be adjusted to a level that jeopardizes the satisfying of the Vtrip, which could therefore cause inoperability of an SRAM. Accordingly, there is a need to further improve aspects relating to circuit and device performance control and energy efficiency with respect to SRAMs and the circuits in which they are included, such as device cores. The preferred embodiments are directed to such improvements.